Metal-insulator-metal (MIM) capacitors are well known. They are typically formed within the interconnect layers of an integrated circuit by depositing a metallic bottom plate, depositing a capacitor dielectric and then depositing, patterning and etching a metallic top plate. Typically to save cost and processing steps the top of bottom plate of the MIM capacitor may be formed using one of the layers of interconnect. For high precision MIM capacitors, however, the top and bottom plates are typically formed using separate metallic layers such as TaN and are not formed using interconnect material.
In a typical process flow for integrating a precision MIM capacitor into an integrated circuit manufacturing flow may add two to three additional via patterning etching steps to accommodate the difference in via depths to underlying interconnect level, to the capacitor bottom plate, and to the via top plate. Typically if one via pattern and etch is used to save cost, a significant yield loss occurs due to etch damage. For example, the via to the capacitor top plate is shallow compared to the to the underlying interconnect. Significant damage to the top plate resulting in yield loss may occur during the time when the top capacitor plate via is open while the bottom plate and interconnect vias are still being etched. Similarly damage to the capacitor bottom plate resulting in yield loss may occur during the time when the bottom capacitor plate via is open while the interconnect via is still being etched.
Embedded metal resistors formed from such material as SiCr are typically less than 50 nm thick. Vias to the resistor heads are typically significantly shallower than the vias to the underlying interconnect. Damage to the resistor heads caused during via overetch when a single via pattern and etch is attempted results in yield loss. To prevent yield loss, typical manufacturing flows with embedded resistors use two via patterns and etching steps or add processing steps to form via landing pads on the resistor heads.